1. Field of the Invention
The present invention relates to a photoelectric conversion device, and more specifically to a MOS type photoelectric conversion device and its manufacturing method.
2. Related Background Art
A demand of a photoelectric conversion device has been rapidly rising in recent years by being used as a photoelectric conversion device of a two-dimensional image input apparatus laying stress on a digital still camera and a video camcorder, or a one-dimensional image reading apparatus laying stress on a facsimile and a scanner.
As the photoelectric conversion device, a CCD and a MOS type photoelectric conversion device are used. As a representative of the MOS type photoelectric conversion device, a CMOS photoelectric conversion device (hereinafter referred to as a “CMOS sensor”) formed by the CMOS process including peripheral circuits has been put to practical use.
FIG. 8 is a circuit composition figure of a pixel of a conventional CMOS sensor. A reference numeral 1 denotes a photodiode (hereinafter referred to as a “PD”) as a photoelectric conversion element converting light into signal charges. A reference numeral 2 denotes a transfer MOS transistor transferring the signal charges generated by the PD 1. A reference numeral 3 denotes a floating diffusion region (hereinafter referred to as an “FD”) for converting the signal charges into a voltage. A reference numeral 4 denotes a reset MOS transistor for resetting the FD 3 and the PD 1. A reference numeral 5 denotes a selector MOS transistor for selecting an arbitrary row in an array. A reference numeral 6 denotes a source follower MOS transistor line of an array and 6 are the source follower MOS transistor for amplifying a signal charge. These components constitute a pixel. A reference numeral 7 denotes a sense line, which is commonly owned by column for reading a pixel signal. A reference numeral 8 denotes a constant current source. One or both of a circuit for processing a signal from the pixel and a drive circuit (shift register) for driving the transistors in the pixel circuit are formed on the same substrate as peripheral circuits, though they are not shown. Each pixel (except for the constant current source 8) is arranged in an array, and constitutes a photoelectric conversion device.
FIG. 9 is a schematic sectional view of a pixel of a photoelectric conversion device mounting the conventional CMOS sensor thereon. In particular, FIG. 9 shows a part of the PD 1 and the transfer MOS transistor 2 in FIG. 8. A reference numeral 11 denotes an N-type silicon substrate. A reference numeral 12 denotes a P-type well. A reference numeral 13a denotes a gate insulation film of a MOS transistor, which is made of a silicon oxide film. A reference numeral 13b denotes a silicon oxide film on a light receiving portion. A reference numeral 14 denotes a gate electrode of the transfer MOS transistor 2. A reference numeral 15 denotes an N-type charge storage region for forming the PD 1. A reference numeral 16 denotes a surface P-type region for making the PD 1 to have an embedded structure. A reference numeral 17 denotes a selection oxide film for element isolation. A reference numeral 18 denotes an N-type impurity region which forms the FD 3 and is also a drain region of the transfer MOS transistor 2. A reference numeral 19 denotes a silicon oxide film insulating the gate electrode 14 and a first wiring layer 21. A reference numeral 20 denotes a contact plug. A reference numeral 22 denotes an interlayer insulation film insulating the first wiring layer 21 and a second wiring layer 23. A reference numeral 24 denotes an interlayer insulation film insulating the second wiring layer 23 and a third wiring layer 25. A reference numeral 26 denotes a passivation film. In a photoelectric conversion device for color use, a not shown color filter layer and further a not shown microlens for improving sensitivity are formed on the upper layer of the passivation film 26. The p-type impurity region 12 and the N-type impurity region 15 constitute a PD 3.
The light having entered the surface enters the PD through an opening portion regulated by the third wiring layer 25. The light is absorbed in the N-type charge storage region 15 or the P-type well 12 of the PD to generate pairs of electrons and holes. The electrons of the pairs are stored in the N-type charge storage region 15. After the storage, by turning on the transfer gate 14, the reading of the electrons into the FD 3, where potential is lower, is performed. After the reading operation, by performing the resetting operation of the N-type charge storage region 15 through the transfer MOS, the N-type charge storage region 15 is completely depleted to a certain voltage. Then, the FD 3 is held at a certain voltage by a similar resetting operation after the turning off of the transfer gate 14.
In the CMOS sensor, in order to efficiently transfer the carriers generated in the PD to the FD 3 through the transfer gate 14 at the time of a reading operation, it is very important to deplete the N-type charge storage region 15 by a desired voltage, especially preferably to completely deplete the N-type charge storage region 15. The depleting voltage is determined by the kind of the photoelectric conversion device, the purpose of use, and the like. Various depleting voltages are set according to the charge quantity which the PD can deal with, a noise characteristic, a drive voltage and the like. These depleting voltages are important parameters influential on the characters of the photoelectric conversion devices.
Simultaneously, the N-type charge storage region 15 is distributed in a form in which the N-type charge storage region 15 is inserted between the surface P-type region 16 and the P-type well 12 in the lower left end part of the transfer gate 14. The density profile of the region 15a is another important parameter influential on the transfer characteristic because the place is a passing road (transfer path 15a) of the charges from the depleted N-type charge storage region 15.
The semiconductor regions such as the surface P-type region and the N-type charge storage region 15, as shown above, receive the performance of patterning by photolithography in a desired region before the semiconductor regions are formed by an ion implantation technique. It is needless to say that the accuracy of energy and a dose quantity for obtaining a desired depleting voltage in good accuracy, as described above.
Moreover, it is necessary that the transfer path 15a mentioned above gets into the lower left end portion of the transfer gate 14 (to be arranged under at least a part of the gate electrode) and is formed in a desired density. Accordingly, the injection is performed to be inclined by a certain angle to the normal line of the mirror surface of a wafer. In this case, it is necessary that the injection is performed uniformly on the wafer surface not only the angle thereof but also the parallelism thereof and the like, and satisfying these necessities are important control techniques for minimizing the dispersion of the desired transfer characteristics.
Moreover, as another parameter for controlling the profile of the ion implantation, there is known a method of performing the ion implantation to a semiconductor substrate from an inclined direction not from the perpendicular direction to reduce the dispersion in the depth direction of the impurity profile caused by channeling.
For example, in the case of performing ion implantation using a semiconductor substrate having a crystal plane (1 0 0) as one principal plane, it is well known that the ion injecting direction may be inclined from the vertical direction by about 7°.
Then, in order to perform the ion implantation itself perpendicularly and to avoid the channeling mentioned above, there have been proposed a method of using a semiconductor substrate having the principal plane thereof inclined (off-angled) by an angle within a range of from 3° to 7° to the crystal plane (1 0 0) (Japanese Patent Application Laid-Open No. H04-343479), a method of using a semiconductor substrate having a plane on which the <1 0 0> axis perpendicular to the crystal plane (1 0 0) is inclined into the direction of (0 1 1) plane and (0 1 1) plane by an angle within a range of from 3.5° to 10° as a principal plane (Japanese Patent Application Laid-Open No. H07-172990; U.S. Pat. No. 5,838,058 (corresponding application in US)), and the like.
Moreover, the channeling can be also suppressed by forming an amorphous film such as an oxide film on the surface of a substrate. In order to avoid contamination caused by a metal or the like, at the time of ion implantation, an oxide film having a thickness of about 10-30 nm is frequently formed on the surface of the substrate. In the conventional process in which ion implantation is performed by the comparatively low energy of about 10-200 keV in a state in which an oxidization film is formed on the surface of a substrate, it is expected that the conventional techniques disclose in the official publications mentioned above demonstrates validity.
Moreover, also in the case where a semiconductor substrate inclined into [0 1 1] direction by 4° is used and ion implantation is performed from the direction perpendicular to the semiconductor substrate, the ion implantation has the similar effects to those of the related art disclosed in the public publications mentioned above. In this case, because an amorphous layer such as a silicon oxide film is formed on the surface of a substrate at the time of ion implantation and thermal processing at a high temperature for a long period is performed after ion implantation, the formation of a comparatively uniform impurity introduction layer is made to be possible.
As described above, although the PD structure of a CMOS type photoelectric conversion device has an advantage of the capability of using the existing CMOS process, the PD structure has several problems for the improvement in an image pick-up performance.
A first problem is the necessity of performing ion implantation after determining an injecting angle so as to satisfy a desired transfer characteristic to a semiconductor substrate. When only caring about projection of photoresist and the like to making the injecting angle perpendicular and performing ion implantation, as shown in Japanese Patent Application Laid-Open Nos. H04-343479 and H07-172990, it is possible to suppress channeling to some extent by inclining the principal plane orientation of a semiconductor board. However, when positioning and density setting with the high accuracy of a semiconductor region which exists under a gate are required like in the case of forming the N-type charge storage region 15, even if the manufacturing methods like the ones disclosed in the Japanese Patent Application Laid-Open Nos. H04-343479 and H07-172990 are used, then highly accurate positioning and density setting become difficult under the influence of channeling. The reason is that, when ion implantation is performed from the direction perpendicular to the principal plane, an off-angle direction is determined not to cause channeling, and that a case where a process of performing ion implantation also from an inclined direction in order to form a semiconductor region in a part under the gate electrode of a transfer MOS transistor is included is not supposed. Because ion implantation is performed under the setting of an injecting angle of combinations in a wide range of from 0 to 45° at the time of forming the N-type charge storage region and the surface P type region of a PD, at some injecting angles channeling cannot be prevented even in a semiconductor substrate including the principal plane inclined in the direction of from the crystal principal plane (1 0 0) to a (0 1 1) plane or from the crystal principal plane (1 0 0) to a (0 1 1) plane like the technique disclosed in Japanese Patent Application Laid-Open No. H07-172990.
A second problem is that the drive voltage of a CMOS sensor has become lower as the degrees of the fineness and the integration of the CMOS sensor has increased, and consequently that the mask oxide film at the time of ion implantation has become thinner and the activation of an impurity profile has become unable to exert the effect up to the degree of cancelling channeling owing to the lowering of the temperature of thermal treatment.
Such tendencies of increasing fineness of processes and the lowering of the temperature are process integration necessary for a future CMOS sensor, and the existing channeling preventing measures seriously hinders the increase of the degree of integration of solid state image pickup elements and the use of a large diameter substrate.
A third problem is that, although the pixel arrangement of an ordinary CMOS sensor is arranged so that pixel pitches may become equal and their directions are also arranged into the same directions, especially in a large-sized CMOS sensor, the layout of a product may become a rectangle owing to the restriction of the drawing area of exposure equipment. In such a case, the directions of PD's and transfer gates are frequently arranged in a layout of being in any one of the directions 90°, 180° and 270° to notches or orientation flats, and the case where the directions do not agree with the optimum solution of channeling is very frequently produced.
It is an object of the present invention to provide a photoelectric conversion device which can realize a PD structure contributing to the improvement of an image pickup performance by regulating the off-angle direction of the principal plane of a semiconductor substrate for forming a photoelectric conversion element, and the formation direction of a semiconductor region constituting the photoelectric conversion element, and its manufacturing method.